1. Field of the Invention
This invention relates to a semiconductor integrated circuit such as a digital signal processor (DSP), a microprocessor or the like, which incorporates a plurality of processing circuits for performing necessary processes therein, and particularly to a semiconductor integrated circuit having a plurality of data holding circuits for respectively effecting logic verification on processing circuits.
2. Description of the Related Art
A semiconductor integrated circuit such as a DSP or a microprocessor has a plurality of processing circuits incorporated therein for respectively performing necessary processes. In the present semiconductor integrated circuit, each of the processing circuits indicates a combinational logic circuit comprised of a combination of logic circuits such as an AND circuit, an OR circuit, etc. A logical level of a signal outputted from the processing circuit is determined to a predetermined logical level according to a logical level of a signal inputted thereto. However, when defects or defective conditions due to a variation with time occur in the processing circuit, the output signal results in a logical level different from a desired logical level with respect to the logical level of the input signal. It is thus of importance that logic verification is effected on the semiconductor integrated circuit having such processing circuits to verify whether or not the processing circuit functions normally.
A plurality of scanpath circuits (also called "scanpath registers") are used in the semiconductor integrated circuit with the objective of executing such logic verification. The scanpath circuits are made up of data holding circuits and the like respectively. Upon a normal operation (i.e., which means the performance of the original processing operation on the signal inputted from the outside of the semiconductor integrated circuit) of the semiconductor integrated circuit, each of the scanpath circuits operates so as to transfer the received input signal to its corresponding processing circuit or output a signal outputted from the corresponding processing circuit to the next-stage circuit. Here, the next-stage circuit is a circuit for receiving the signal outputted from the processing circuit therein and effecting desired processing on it. Upon operation for effecting the logic verification on the corresponding processing circuit, the scanpath circuits constitute shift registers provided in cascade connections.
As a circuit configuration of each scanpath circuit, one is known which has heretofore been disclosed in the following reference:
Japanese Patent Application Laid-Open No. 05-150003. PA1 a plurality of processing circuits for respectively executing necessary processes; PA1 a plurality of data holding circuits respectively provided so as to correspond to the plurality of processing circuits, the plurality of data holding circuits being respectively activated independently upon a first operating mode and activated as shift registers by being cascade-connected upon a second operating mode; PA1 each data holding circuit including, PA1 a first clock input terminal supplied with a first clock signal employed in a first operating mode; PA1 a second clock input terminal supplied with a second clock signal employed in a second operating mode; PA1 an operating mode input terminal supplied with an operating mode setting signal for performing switching between the first operating mode and the second operating mode; and PA1 a control signal generating circuit for generating and outputting at least the first and second control signals, based on states of the signals inputted to the respective input terminals and outputting either the first or second clock signal as the clock signal received by each data holding circuit. The above object can be achieved by this construction.
Various demands have recently been made to the semiconductor integrated circuit. It is desired to bring the semiconductor integrated circuit into less size as one of the demands. One method of achieving this object or purpose is to reduce the scale of circuits incorporated into the semiconductor integrated circuit.
It is also desirable to reduce power consumption as another demand.
It is desired to make a reduction in clock skew (timing shift of a clock signal) as a further demand. Namely, since a plurality of scanpath circuits are connected in tandem so as to constitute shift registers, it is necessary to activate all the scanpath circuits in synchronism with each other.
As a still further demand, the storage of a predetermined initial value in a control register or a flag register or the like upon resetting of hardware is essential for the semiconductor integrated circuit if the semiconductor integrated circuit is the DSP or the microprocessor or the like.
There is often a still further demand for always supplying a clock signal to each scanpath circuit and storing therein a data signal inputted as needed.
The scanpath circuit disclosed in the above-described reference did not necessarily meet these demands. It has therefore been desired to allow the advent of a scanpath circuit for satisfying the above-described demands.